1. Technical Field
The present disclosure relates to a hot electron injection MOS transistor, comprising source and drain regions implanted in a semiconductor substrate, a control gate, and a floating gate arranged between the control gate and the substrate to accumulate electrical charges.
2. Description of the Related Art
Conventionally, FLASH memories comprise MOS (Metal Oxide Semiconductor) transistors of the type cited above. The programming of such transistors is done in the presence of a high drain-source current using an injection of electrical charges into the floating gate called “hot electron injection”. Erasing of the transistors is done however in a static manner by tunnel effect (also known as the Fowler-Nordheim effect), by applying biasing voltages to the transistors to extract the charges trapped in the floating gate without causing current to flow between the drain and the source.
It is known that hot electron injection transistors have a low injection efficiency, and a high programming current. This property limits the number of transistors that may be simultaneously programmed in a memory, generally 8, 16, or 32 transistors. In low-power consumption semiconductor products, the number of transistors that can be simultaneously programmed is however dictated by current consumption limitations.
FIGS. 1, 2, and 3 are cross-sectional views of conventional hot electron injection MOS transistor structures T1, T2, T3.
Transistor T1 comprises a P-type substrate 1, N-type source (S) 2 and drain (D) 3 regions, a floating gate FG1, and a control gate CG1. Floating gate FG1 and control gate CG1 are generally in polysilicon (polycrystalline silicon). Control gate CG1 and source 2 and drain 3 regions are provided with electrical contacts schematically shown in FIG. 1. Floating gate FG1 is electrically isolated from substrate 1 and from control gate CG1 by a dielectric material 10.
The programming of transistor T1 is done by applying a positive voltage VD to drain region 3, a positive voltage VCG to control gate CG1, and a zero (ground or GND) voltage VS to source region 2, these voltages being chosen so as to set the transistor in a saturated operating mode. The gate voltage VCG causes a vertical electrical field EV to appear. Electrical field EV causes an inversion zone 5 to appear in the substrate 1, forming a conductive N-type channel through which the electrons may flow, and which has a pinch-off zone 6 near drain region 3. The drain-source potential difference causes a current IDS to appear between drain region 3 and source region 2, corresponding to a flow of electrons traveling in the opposite direction between source region 2 and drain region 3. At pinch-off zone 6, the electrons have a high kinetic energy. The majority are propelled into drain region 3 whereas a small amount have a sufficient kinetic energy to reach the potential barrier of dielectric material 10 and penetrate into floating gate FG1, where they are trapped. The region of substrate 1 extending between pinch-off zone 6 and drain region 3 is also called the injection zone 7.
The electrical charges trapped in floating gate FG1 modify the threshold voltage of the transistor. This threshold voltage may then be measured by a sense amplifier, the output of which supplies a logical value 0 or 1 depending on whether the transistor is in the programmed or non-programmed state (the non-programmed state known as the erased state).
As indicated above, such a transistor structure T1 has a low injection efficiency, typically on the order of 10−5 to 10−6. The injection efficiency is conventionally the ratio between current IDS during programming and the current injected in the floating gate (the quantity of trapped electrical charges being equal to the injected current multiplied by the injection time).
This low efficiency can be explained by a high attenuation of the vertical electrical field EV near injection zone 7. This field is high around source region 2 but decreases as drain region 3 is approached, as it is neutralized by drain voltage VD, which also causes pinching of the channel.
Transistor structure T2 shown in FIG. 2 differs from that of FIG. 1 by the fact that it has a nanocrystal floating gate structure NCFG1. Floating gate NCFG1 is made from a dielectric material 11 in which electrically conductive nanoparticles 12, for example of silicon or germanium, are embedded. These conductive particles 12 can accumulate electrical charges that modify the threshold voltage of the transistor, and have the same function as a conventional floating gate. The programming of transistor T2 is done in a manner similar to that indicated above, and the injection efficiency is equally low.
It may therefore be desired to provide a hot electron injection MOS transistor structure that has a higher injection efficiency than those shown in FIGS. 1 and 2.